Mathematical algorithms, such as my favorite DSP filtering algorithms, all Purpose, number crunching is certainly one of the basic ones.
You know, those serious number crunching applications. You could perhaps make a tree module where you can specify which layer(s) have pipes, and that could be fun but its a bit tricky and probably not work it right now (you'd use a generate then to either make count a flop or combinatorial at each layer, so you could say add a flop at the input then every two layers, or something).One of the basic purposes of FPGAs is to run algorithms, and to run them fast. I think you'll find it essentially synthesizes identically to a for loop. Wire ready_e1 = ~rst & (a_shifted = 0 || a_shifted = 1) // technically if a _shifted is 1 now, we will finish this clock, so ready can be high next cycle)Īlways_ff clk) a_shifted <= rst ? '0 : load_data ? a :
(One quick thing to note that your output 'ones' has more bits than is needed, Ie say you have 16 bits, the maximum output you could have is 16, which is log2c(16 + 1) - most verilog/system verilog support the system function $clog2() so you could make ones have a width of $clog2(N).įor style, I might write your code more like this (not tested, but it shows some style a bit better) module one_bit_counter# ( Your design has bad throughput and latency but should use very little resources, low power, low area, and should timing easily. This may or may not be okay in application, in Digital design its often times a tradeoff between throughput, latency (the two can be different if you pipeline), power, area, and meeting timing. That means that you use very few resources, but your throughput is limited to one input per N cycles. Your design essentially adds 1 bit per clock, and is not pipelined. Thank youĪ_rotated > 1 //rotated right by one, insert zero from the MSBĪssign ready = ~|a_rotated //if no more ones in a_rotated, ready is asserted In parallel to the link above, I'm attaching the code here as well. Then I go over each bit until no more ones in the captured value. *I'm capturing the bus when data is valid. It works.īut can this be synthesis? and would apricate any input if you see anything that can be done/written better or even enlighten me, methodically wise. (not school or work related, just playing with EDA). Hi, I've wrote a code in systemverilog which counts how many bits are equal to '1 in a bus.
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